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Qualcomm SA8155P: Automotive Development Platform Guide

Qualcomm SA8155P: Automotive Development Platform Guide

March 09 , 2023 Posted by KUKE 0

SA8155P is an integrated, next-generation automotive cockpit platform. It is programmable means that its function can be changed by computer instructions. It not only has 3 programmable parallel I/O interfaces (port A and port B are 8-bit, port C is 6-bit), but also has 256b SRAM and a 14-bit timer/counter, which are often used as external expansion of the microcontroller interface to connect with peripheral devices such as keyboards and monitors.

SA8155P Specifications

1) CPU
• Custom 64-bit Kryo octa-core CPU
• 7nm FINFET with advanced power savings
• SOC virtualization support
• 384 KB L1 I/D + 1.875 MB L2 + 2 MB L3 + 3 MB system cache

2) GPU
• Adreno 640 GPU: OpenGL ES 3.x OpenCL 2.0 Full, Vulkan, RenderScript, 64-bit virtual addressing, plus hardware tessellation,geometry shaders,programmable blending,and decreased power consumption
• High granularity for preemption with HW queues and doorbell features

3) DSP + NPU
• Qualcomm® Hexagon™ 6 DSP with Hexagon Vector eXtensions (HVX)—Four instances
• Neural Processing Engine (NPU) for machine learning acceleration

4) Audio DSP and Audio Interfaces
• Dedicated Audio Low Power Audio Subsystem (LPASS) with Hexagon 6 DSP
• Support for ECNS, ANC, and in-car communication using Qualcomm® Noise and Echo Cancellation
• 5 interfaces supporting I2S and PCM/TDM
• Up to 512* 48 kHz (24.576 MHz)
• 3x high-speed I2S (70 MHz) to support Software Defined Radio (SDR)

5) Display and Video Processing
• Up to 3x 4kp60 support—Total of 24 Mpix supported in HW display compositor
• Support for 2x DSI V1.0 and DisplayPort V1.4 with Multi-Stream Transport (MST) support (up to 2x 4k60)
• Multiple surface processing pipes
• Support for instrument cluster integrity
• Hardware video decode/encode support—Up to 4k120 decode, 4k60 encode support
• Support for major video codecs (HEVC, H.264/H.265, etc.)

6) Memory and Storage
• 4x16 LPDDR4X support—Up to 68 GBps with compression (Gen 3 of UBWC)
• Error Correction Code (ECC) support on external memory
• 1x UFS 3.0 support
• QSPI for boot

7) Camera and ISP Support
• Support for automotive ISP
• 4x4 CSI 2.0 lane for camera support
• Support for Around View Monitoring (AVM) and Rear-View Camera (RVC) with automotive enhancements

8) Interfaces and I/O
• 1x 2-lane PCIe Gen3 + 1x 1-lane PCIe Gen3
• 2x USB3.0 support—Host and endpoint
• 1x GigE with RGMII support
• Up to 16 programmable serial interfaces
• 150 general purpose I/Os

9) Connectivity
• Dual-band 802.11ac Wi-Fi and Bluetooth 5.0
• 1x Ethernet port
• 4x CAN

10) Integrated Communication Support(optional)
• Integrated 4G LTE modem
• 10xCA, 4x4 over 4xCA, UL 4xCA—Up to 2 Gbps of bandwidth
• Multi-constellation and multi-level (L1/L5) support
• IPA for Ethernet and modem built in

11) Security
• Secure boot using RSA2048/SHA256,boot image encryption
• HW and SW encryption including inline crypto, RNG and general-purpose crypto engine
• Qualcomm® Trusted Execution Environment (TEE) support
• Dedicated security HW SPU for auto applications

12) OS Supported
• Android Automotive
• Linux—AGL, GENIVI
• Hypervisor including QNX and Green Hills

13) Power Management
• Power Management IC—PMM8155AU providing power management for SA8155P
• RTC, power-down and wake-up support
• PWM support
• AEC-Q100 Grade-3

14) Power and Thermal
• -40° to 105°C junction temperature support
• Estimated TDP of 7 W (at 65°C ambient)
• Support for always-on/suspend to RAM

15) Power Supply
• 12V DC Automotive Spec and Package
• AEC-Q100 Grade-3
• 0.7 mm ball pitch package—23mm x 23mm 989 ball FCBGA package
• In production, PPAP and documentation available

SA8155P User Manual

SA8155P I/O Ports Description

Figure 1: 8155 Pinouts

RESET: Reset signal input terminal, high level . After reset, the 3 I/O ports are input mode.
AD0-AD7: Three-state address/data bus. It is connected with the low 8-bit address/data bus (port P0) of the microcontroller. The address, data, command and status information between the them are all transmitted through this bus port.
RD: Read strobe signal, control the read operation of 8155, low level.
WR: Write strobe signal, control the write operation to 8155, low level.
CE: Chip select signal line, low level.
When IO/M = 0, select the on-chip RAM, and the address on AD0~AD7 is the address of the RAM unit in 8155 (00H~FFH).
When IO/M = 1, select the I/O port of SA8155P, and the address on AD0~AD7 is the address of 8155 I/O port.
ALE: Address latch signal, there is an address latch inside the 8155, and the low 8-bit address information output by the P0 port of the microcontroller and the state of I/O are latched to the internal latch of the 8155 at the falling edge of ALE. Therefore, the low 8-bit address signal output by port P0 does not need an external latch.
PA0-PA7: 8-bit general-purpose I/O ports, the flow direction of its input and output can be controlled by the program.
PB0～PB7: 8-bit general-purpose I/O port, the function is the same as port A.
PC0～PC5: There are two functions, they can be used as general-purpose I/O ports, and can also be used as control signal lines of PA port and PB port, which can be controlled by program.
TIMER IN: Timer/counter pulse input.
TIMER OUT: Timer/counter output.
VCC: +5V power supply.

SA8155P Address Code and Working Method

In the single-chip microcomputer application system, 8155 is uniformly addressed according to the external data memory, which is 16-bit, and its upper 8 bits are provided by the chip selection line, CE=0, select the chip.
When CE=0, IO/M=0, select 8155 on-chip RAM, then 8155 can only be used as off-chip RAM, and the address of the lower 8 bits of RAM is 00H～FFH;
When CE=0, IO/M=1, the I/O port of 8155 is selected, and the lower 8 bits of the port address are determined by AD7~AD0, as shown in the table 1. At this time, the lower 8 bits of the port addresses of ports A, B, and C are 01H, 02H, and 03H respectively (set the irrelevant bit of the address to 0).
Table 1: I/O Port Address of 8155 Chip

A7	A6	A5	A4	A3	A2	A1	A0	I/O Ports Selection
×	×	×	×	×	0	0	0	Command/Status Register Port A Port B Port C The lower 8 bits of the timer The upper 6 bits ot the timer and mode
×	×	×	×	×	0	0	1
×	×	×	×	×	0	1	0
×	×	×	×	×	0	1	1
×	×	×	×	×	1	0	0
×	×	×	×	×	1	0	1

The PA and PB of 8155 can work in basic I/O mode or strobe I/O mode. PC can work in the basic I/O mode, and can also be used as a state control signal line for A and B in the strobe mode. When P C is used as a state control signal, the function of each bit line is as follows:
PC0: AINTR (PA interrupt request line)
PC1: ABF (PA buffer full signal )
PC3: BINTR (PB interrupt request line)
PC4: BBF (PB buffer full signal)
The I/O working mode selection of 8155 is realized by setting the control word to the internal command register. The command register can only be written in and cannot be read out. The format of the command register is shown in Figure 2.

Figure 2: Command Register Format

Under the different modes of ALT1~ALT4, the working modes of the PA, PB and PC are as follows:
ALT1: PA, PB is the basic input/output, PC is the input mode.
ALT2: PA, PB is the basic input/output, PC is the output mode.
ALT3: PA is strobe input/output, PB is basic input/output. PC0 is AINTR, PC1 is ABF, and PC3-PC5 are outputs.
ALT4: Port A and port B are strobe input/output. PC0 is AINTR, PC1 is ABF, PC3 is BINTR, and PC4 is BBF.
The format of the SA8155P status register is shown in Figure 3:

Figure 3: Status Register Format

SA8155P vs SA8195P

Feature set		Example use case		SA8155P	SA8195P
Process node				7nm	7nm
CPU type	Cores and frequency		Number and core frequency	Octa core Kryo 485 with ECC 3x gold – 2.131 GHz 1x gold prime – 2.419 GHz 4x silver – 1.785 GHz	Octa core Kryo 495 with ECC 4x gold prime – 2.496 GHz 4x silver – 1.7664 GHz
			Cache	Gold – 256 KB L2 per core Gold prime – 512 KB L2 Silver – 128 KB L2 per core Shared – 2 MB L3	Gold prime – 512 KB L2 per core Silver – 128 KB L2 per core Shared – 4 MB L3
Graphics		Frequency		Adreno 640 700 MHz	Adreno 680 675 MHz
Memory architecture		Architecture/speed		4 × 16, 2092.8 MHz LPDDR4X with ECC	8 × 16, 2092.8 MHz LPDDR4X with ECC
Temperature rating		Junction range		-40°C to 105°C	-40°C to 105°C
DSP	Audio DSP		Audio processing	Q6 V66J (2 threads/2 clusters, 512 KB L2) at 1.4592 GHz	Q6 V66J (2 threads/2 clusters, 512 KB L2) at 1.4592 GHz
	General purpose DSP		Advanced audio processing	Q6 V66B (2 threads/1 cluster, 1536 KB L2) at 1.4592 GHz	Q6 V66B (2 threads/1 cluster,1536 KB L2) at 1.4592 GHz
	Compute DSP		Compute processing	Q6 V66G (4 threads/2 clusters, 1024 KB L2, 4x HVX) with ECC 1.4592 GHz	Q6 V66G (4 threads/2 clusters, 1024 KB L2, 4x HVX) with ECC 1.4592 GHz
	NPU		Neural processing	NPU130 with ECC 908 MHz	NPU130 with ECC 908 MHz
	Modem DSP		Modem processing	Scalar Q6 V66H (4 threads/2 clusters, 1.5 MB L2) at 1.4592 GHz Vector Q6 V66U (4 threads/ 2 clusters, 512 KB L2) at 1.4592 GHz	Scalar Q6 V66H (4 threads/ 2 clusters, 1.5 MB L2) at 1.4592 GHz Vector Q6 V66U (4 threads/ 2 clusters, 512 KB L2) at 1.4592 GHz
Multimedia	Display		Multiple displays with scalable resolution	3x 4K or 4x 2K	3x 5K
	Video		Video decode/encode concurrent	4K120/4K60 4K60/4K30	4K120/4K60 4K60/4K30
	Camera		Multiple concurrent camera input streams	2.5 Gbps/lane, up to 40 Gbps total	2.5 Gbps/lane, up to 40 Gbps total
Safety				Safety Element Out of Context (SEooC) targeting assumed system level ASIL-B user cases	Safety Element Out of Context (SEooC) targeting assumed system level ASIL-B user cases

I/O		Description	SA8155P	SA8195P
Memory	EBI		LPDDR4X 4x 16 bit 2092 MHz	LPDDR4X 8x 16 bit 2092 MHz
	SD/eMMC		SD 3.0 − 4-bit SDC2 − 4-bit SDC4	SD 3.0 − 4-bit SDC2 − 4-bit SDC4
	UFS		2 lane UFS 2.1 gear 3	2x 2 lane UFS 3.0 gear 4 rate A
	Quad-SPI		1x 4 lane (2x CS)	2x 4 lane (2x CS)
Display	DSI		DSI D-PHY v1.2 4-lane DSI0 4-lane DSI1	DSI D-PHY v1.2 4-lane DSI0 4-lane DSI1
	DisplayPort		4-lane DisplayPort v1.4 shared with USB 3.1 Gen 2	3x 4-lane DisplayPort v1.4, 2x shared with USB 3.1 Gen 2 1x 4-lane embedded DisplayPort v1.4b
Camera	CSI		CSI-2 v1.3 4-lane CSI0 4-lane CSI1 4-lane CSI2 4-lane CSI3	CSI-2 v1.3 4-lane CSI0 4-lane CSI1 4-lane CSI2 4-lane CSI3
Broadcast	TSIF		2x	2x
High-speed interfaces	USB		1x USB 3.1 Gen 2 with DisplayPort 1x USB 3.1 Gen 2	1x USB 3.1 Gen 2 with DisplayPort 1x USB 3.1 Gen 2
	PCIe		2-lane PCIe 3 (RC/EP) 1-lane PCIe 3 (RC)	1x 1-lane PCIe 3 (RC) 2x 2-lane PCIe 3 (RC) 1x 4-lane PCIe 3 (RC/EP)
	RGMII/RMII		1x with MDIO 1.8 V only	1x with MDIO 1.8 V only
Audio	LS-I2S		4x 2 data lanes 1x 4 data lanes	4x 2 data lanes 1x 4 data lanes
	HS-I2S		3x 2 data lanes, receive only	3x 2 data lanes, receive only
	TDM/PCM		5x	5x
Miscellaneous	SPI I2C I3C UART		26x QUP SE (GPIO + SSC) SPI – master and slave I2C – master I3C – master UART – host	26x QUP SE (GPIO + SSC) SPI – master and slave I2C – master I3C – master UART – host
	GPIO		174	190

All SA8155P specifications are listed here, but not all features listed may be supported in software you used. If you have any questions, please consult the official staff. And if you need related components, just visit KUKE ELECTRONICS.

Qualcomm SA8155P: Automotive Development Platform Guide

SA8155P Specifications

SA8155P User Manual

SA8155P Address Code and Working Method

SA8155P vs SA8195P

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