RISC-V Basic and Related Open Source Professors

Why RISC-V? 

RISC-V (pronounced "RISC-FIVE") is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC), where “V” represents the fifth generation of RISC. So there have been four gens of RISC processor prototype chips before. Each generation of RISC processors has been led by Professor David Patterson of the University of California, Berkeley. Its goal is to become Linux in the field of instruction set architecture, with applications covering IoT (Internet of Things), desktop computers, high-performance computers, and many other fields.

RISC-V was produced because UCB researchers found the following problems in the current architectures.

(1) Most instruction set architectures are protected by patents, such as: x86, MIPS, and Alpha. The use of these architectures requires authorization, which limits competition and reduces innovation.

(2) The current architecture is relatively complex and not suitable for academic research, and a lot of complexity is caused by some poor designs.

(3) They aimed at a certain field. For example, x86 is mainly oriented to servers, and ARM is mainly oriented to mobile terminals. For this reason, the corresponding architecture has done a lot of domain-specific optimization for this field. So there is no unified one can apply to multiple domains.

(4) The commercial architecture is easily affected by the development status of the enterprise. For example, the Alpha architecture almost disappeared with the acquisition of DEC.

(5) The existing architectures are not convenient for custom extensions for specific applications.

According to these shortcomings, UCB researchers Krste Asanovic, Andrew Waterman, and Yunsup Lee decided to design a new instruction-level architecture. Open source with BSD authorization, hoping that more innovative processors will be produced, and the cost of electronic products will be reduced.

Since its official release in 2014, RISC-V has been supported by many companies including Google, IBM, Oracle, etc., as well as many well-known universities and research institutions including Cambridge University, ETH Zurich, Indian Institute of Technology, and Chinese Academy of Sciences. The ecological environment surrounding RISC-V is also gradually improving, and many open source processors and SoCs have emerged using the RISC-V architecture. These processors are both scalar or superscalar, and single-core or multi-core. The following article will briefly introduce the basic design of the RISC-V architecture, open source processors and SoCs based on RISC-V architecture.

RISC-V Basic

RISC-V is a typical three-operand, load-store form, including three basic instruction sets and six extended instruction sets, of which RV32E is a subset of RV32I and is not calculated separately.

	Name	Instruction count	Description
Base	RV32I	47	Base Integer Instruction Set, 32-bit
	RV32E	47	Base Integer Instruction Set (embedded), 32-bit, 16 registers
	RV64I	59	Base Integer Instruction Set, 64-bit, 32 registers
	RV128I	71	Base Integer Instruction Set, 128-bit, 32 registers
Extension	M	8	Standard Extension for Integer Multiplication and Division
	A	11	Standard Extension for Atomic Instructions
	F	26	Standard Extension for Single-Precision Floating-Point
	D	26	Standard Extension for Double-Precision Floating-Point
	Q	26	Standard Extension for Quad-Precision Floating-Point
	C	46	Standard Extension for Compressed Instructions

The name suffix of the basic instruction set is I, which means "Integer". Any processor using the RISC-V must implement a basic instruction set, and can implement a variety of extensions. For example: If RV32IM is implemented, it includes the 32-bit basic instruction set and the multiplication and division extensions. If it is RV32IMAFD, also called RV32G, it is a general-purpose scalar processor instruction set. Here is a basic introduction to the situation of RV32I.

The RV32I has 47 instructions, which can meet the basic requirements of modern operating systems. They can be divided into the following categories according to their functions.

1) Base Integer Instruction Set: realize arithmetic, logic, comparison and other operations.

2) Branch Transfer Instructions: conditional or unconditional transfer, and no delay slot.

3) Load and Store Instructions: include bytes, halfwords, and words, and the relative addressing mode of registers is adopted.

4) Control and Status Register Access Instructions: realize atomic read-write, read-modify, read-clear and other operations on system control and status registers.

5) System Call Instructions: realize system call, debugging and other functions.

The RISC-V has three working modes:

1) Machine (M) Mode

2) Supervisor (S) Mode

3) User (U) Mode

The M Mode is mandatory, and the others are optional. Different systems can be realized by combining different modes.

The RISC-V defines some control and status registers (CSR), which are used to configure or record some running status. The CSR register is inside the processor core, and its own address encoding space has nothing to do with the memory addressing.

In addition, CSR registers are accessed using dedicated instructions, including CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, and CSRRCI.

Interrupt and exception mechanisms are often the most complex and critical parts of the processor. However the RISC-V is relative simple, and allows users to customize and extend it.

The RISC-V supports third-party extensions, and it reserves a large amount of encoding space for user-defined extensions. What's more, four custom instructions are defined for users directly, and each one has several bits of sub-coding space to use. Therefore, users can directly use them to expand dozens of custom instructions.

1) Easy to operate.

2) Support modular and configurable instruction sets.

3) Support self-custom instructions.

4) Instructions are streamlined and not redundant.

     * Only little-end formats are supported.

     * Memory access only one element at a time

     * Have the instruction increment and decrement mode of the memory access.

     * Regular instruction encoding format

     * Simplified branch jump instructions and static prediction mechanism

     * Do not use branch delay delay slot.

     * Do not use conditional code.

     * Do not generate an exception.

     * 16-bit compressed instructions have corresponding 32-bit instructions.

     * Do not use zero-overhead hardware loops.

Research Status of Open Source Processors for RISC-V

At present, there are many open-source processors(CPU) based on the RISC-V, including the Rocket, the BOOM, or the Z-scale and the PicoRV32 (embedded).

Rocket is a 64-bit, 5-stage pipeline, single-issue sequential CPU designed by UCB. The main features are:

1) Support MMU and paging virtual memory, so you can transplant Linux operating system.

2) Have FPU that is compatible with IEEE 754-2008 standard.

3) Have branch prediction function, with BTB (Branch Prediction Buff), BHT (Branch History Table), RAS (Return Address Stack).

Rocket is written in Chisel (Constructing Hardware in an Scala Embedded Language), which is an open-source hardware programming language designed by UCB. It is a domain-specific application of the Scala language and has its advantages. More over, Chisel introduces concepts such as object orientation, functional programming, parameterized types, and type inference into hardware programming languages to become powerful.

Also, Chisel has an advantage that using hardware circuits, so you can get the corresponding Verilog design through compilation, even the corresponding C++ simulator. Because of Chisel’s advantages, Rocket can be easily obtain the corresponding software simulator, at the same time, it can be directly used by other open-source CPUs and SoCs.

BOOM is a 64-bit superscalar and out-of-order execution processor designed by UCB. It supports RV64G and is also written in Chisel. Taking advantage of Chisel, it only uses 9000 lines of code, and the pipeline can be divided six stages: instruction fetch, decode/rename/instruction allocation, launch/read register, execution, memory access, and write back.

BOOM is synthesizable and parameterizable, the parameters include:

1) Instruction fetching, decoding, submitting, and issuing.

2) Re-Order Buffer (ROB), the size of the physical register

3) Instruction fetching cache, RAS, BTB, load, store queue

4) Orderly or disorderly emission

5) The numbers of L1 cache

6) The size of MSHRs (miss status handling registers)

7) Whether to enable L2 cache

UCB has taped out BOOM on the 40nm process. It can be seen that the performance of BOOM and the commercial product ARM Cortex-A9 is slightly better, which is reflected in the small size and low power consumption.

SHAKTI is a project of the Indian Institute of Technology. Its goal is to design a series of RISC-V-based open source processors suitable for different application environments, as well as some IP cores to build SoC. These processors are E-Class, C-Class, I-Class, M-Class, S-Class, H-Class, T-Class, N-Class, the first three are currently open, using Bluespec System Verilog.

1) E-Class: 32-bit, 3-stage pipeline, supports C (Compress) extension of RISC-V, and ultra-low power consumption.

2) C-Class: 32-bit or 64-bit, 3-8-stage pipeline, supports MMU, C extension of RISC-V, ultra-low power consumption, and has fault tolerance function.

3) I-Class: general-purpose, 64-bit, 1-8 cores, out-of-order machine, shared L2 Cache, supports dual threads, and SIMD/VPU.

4) M-Class: An enhanced version of I-Class, which increases the instruction launch size, supports four threads, up to 16 cores. It aims to general-purpose processors, low-end servers, and mobile applications.

5) S-Class: 64-bit, L3 Cache, RapidIO, HMC (Hybrid Memory Cube), vector processing unit, and coprocessor for database access, encryption algorithm, machine learning, up to 64 cores. It targets general-purpose processors and servers.

6) H-Class: 64-bit, 32~128-core, multi-threaded, sequential or out-of-order machine, with a vector processing unit. It aims at high-performance computing.

7) T-Class: 64 or 128-bit. It introduces the tag for the memory security.

8) N-Class: Its goal is to process network data through self-custom extensions.

PicoRV32 is a 32-bit MCU designed by VectorBlox. The goal is to apply to the embedded field. It is written in VHDL and implements RV32IM. And it can also remove the M extension, that is, remove the multiplication and division extension, so as to reduce the resource occupation of the chip, and even remove the instructions related to the timer, thus only RV32E is implemented.

RI5CY is a compact 4-stage pipeline open source processor jointly designed by ETH Zurich and University of Bologna, which implements RV32IC and the multiplication instruction mul in RV32M. Its goal is to serve as the processor core of the parallel ultra-low power processor PULP. It has added many extensions in SystemVerilog, including hardware loops, multiply and accumulate, advanced arithmetic instructions, etc. Use UMC's 65nm process for tape-out, the main frequency can reach 654MHz, and the dynamic power consumption is 17.5uW/MHz.

RIDECORE (RISC-V Dynamic Execution CORE) is a out-of-order machine designed and released by Tokyo Institute of Technology. It realizes RV32IM, 6-stage pipeline, which are instruction fetching, decoding, instruction distribution, launch, execution, and submission. It can fetch, decode, and submit two two instructions at the same time in Gshare branch prediction mechanism.

Hwacha is a vector processor developed by UCB, as a non-standard extension Xhwacha of RISC-V. It has been taped out many times with 28nm and 45nm processes, and the main frequency is above 1.5GHz. It is still under study, like modifying the OpenCL compiler to suit Hwacha, and UCB plans to release its code as open source.

f32c is a 32-bit, 5-stage pipeline, scalar processor designed and released by the University of Zagreb. It originally implemented the MIPS instruction set, and later added the RISC-V. The processor includes branch prediction, direct mapping cache, and also released SDRAM controller, SRAM controller, video FrameBuffer, SPI controller, UART, GPIO and other IPs in VHDL. Using the f32c processor core, the University of Zagreb released the FPGA Arduino project, which turns an FPGA development board into an Arduino board, and can use the Arduino IDE to compile and download programs.

Z-scale is a 32-bit, 3-stage pipeline, single-issue scalar CPU released by UCB for embedded environments, and it implements RV32IM. While the instruction bus and data bus are both AHB-Lite. It uses code written by Chisel, using the code in Rocket, only 604 lines of code are added. In addition, V-scale is the Verilog version corresponding to Z-scale.

sodor is a 32-bit open source processor series released by UCB for teaching. It is implemented by Chisel, and the corresponding C++ simulator can be easily obtained. There are five types of processors in the sodor series, which are single-cycle, 2-stage pipeline, 3-stage pipeline, 5-stage pipeline processors that can execute microcode.

cPicoRV32 is an optimized open source processor designed and released by RISC-V developer Clifford Wolf. It implements RV32IMC and can be configured to implement RV32E, RV32I, RV32IC, RV32IM, and RV32IMC according to different environments. An optional interrupt controller is built in. It is characterized by small size, occupies 750-2000 LUTs on Xilinx7 series chips, and the speed can reach 250-400MHz. PicoRV32 is coded in Verilog.

Tom Thumb is a 32-bit, 6-stage pipeline, RV32I open source processor designed and released by maikmerten. The goal is to minimize the resource occupation of FPGA. It occupies about 1200 LEs on Cyclone IV series FPGA in VHDL.

FlexPRET is a 5-stage pipeline and multi-threaded processor designed and released by UCB in Chisel. It is aimed at real-time embedded applications, and the number of threads can be configured from 1-8. In order to improve the resource utilization, each hardware thread is marked as hard real-time thread or soft real-time thread, and the former is scheduled according to a fixed frequency.

YARVI (Yet Another RISC-V Implementation) is a simple, 32-bit designed and released by RISC-V developer Tommy Thorn, which implements RV32I and uses Verilog. Its starting point is not performance, but to be able to realize RV32I accurately.

Research Status of Open-source SoC Based on RISC-V

In order to facilitate users' learning and to reuse the designed hardware modules, UCB established the Rocket-Chip Generator project on GitHub, which includes Chisel, GCC, Rocket processors, and a series of bus units, peripherals, cache, etc., and adopts a parameterized configuration method, so that it is convenient to create SoCs based on Rocket processors with different performance requirements. Written in Chisel, the main sub-modules are as follows.

Chisel: An open source hardware programming language designed by UCB.

Hardfloat: A floating-point unit compliant with the IEEE 754-2008 standard with configurable parameters.

Riscv-tools: Development tools, including GCC, Newlib, and ported Linux.

Rocket: include L1 Cache.

Uncore: Implements functional units that need to be closely connected with Rocket, such as L2 Cache, L1 Coherence Hub, etc.

Juntions: Have conversion between interfaces of different protocols.

Rocketchip: The top-level module also realizes the conversion of the internal bus TileLink to the external bus AXI or AHB.

In addition, the BOOM and Z-scale introduced above can be obtained by configuring different parameters of the Rocket-Chip.

LowRISC is a non-profit organization established by some R&D personnel mainly from Cambridge University. It mainly designs and releases 64-bit open source SoC based on RISC-V. Its goal is to make SoC cheap, feature-rich, and has a large number of users similar to the Raspberry Pi. For example, LowRISC, one of their works, which is improved and developed on the basis of Rocket-Chip using System Verilog. The main features are:

(1) Tagged Memory: A tag is added to each storage location: a double word (64-bit) corresponds to a Tag (4-bit). The purpose is to prevent control flow hijacking attacks, and it also has other uses, such as: garbage collection, watchpoint set, etc. Because of it, LowRISC adds two instructions to RISC-V to read and write tags. This feature is available in version 0.1 released in April 2015.

(2) Untethered: Early Rocket-Chip needs to rely on the assistance of a general-purpose processor to start and access serial ports, network ports, SD cards and other peripherals. Untethered LowRISC implements uses on-chip Functions such as NASTI interconnect solve the above problems. This feature is available in version 0.2 released in November 2015.

(3) Trace Debugging: Introducing Open SoC Debug, Trace Debugging can collect instruction execution records for offline or online analysis. This feature is available in version 0.3 released in July 2016.

PULPino is a RISC-V open source processor jointly released by ETH Zurich and Bologna University. The project they originally designed was PULP, which is a multi-core SoC project. Considering that this project is too complicated, and there are many IP and custom tool sets are not convenient to open source, so the developers decided to do a single-core SoC project, namely PULPino, which directly uses many IPs of the PULP project.

PULPino has an AXI interconnect bus and an APB bus to connect low-speed peripherals, such as: GPIO, UART, I2C controller, SPI Master controller, etc. The debug module supports advanced debug unit. PULPino includes a Boot ROM, which can be written into the BootLoader, so that the program can be read from the external flash memory and executed at startup.

RISC-V VHDL is a Rocket-based open source SoC released by Russia's GNSS Sensor company, and its predecessor is a project of the Moscow Institute of Physics and Technology. The processor core of this project directly uses Rocket, which can be configured to include only L1Cache or L2 Cache. On this basis, a large number of IP cores are provided, using the GRLIB library similar to LEON3. Where cores are plugged in directly to use, in addition, RISC-V VHDL provides an AXI bus, IP cores are mounted on the bus. The IP core includes UART, GPIO, interrupt controller, ethernet controller, and also supports DSU (debug support unit), all of which are written in VHDL.

Most of the IP cores in RISC-V VHDL are open source, and the commercial one is GNSSLIB, which is a library related to positioning and navigation.

Development of RISC-V

With the time went by, RISC-V has breakthroughs in the following aspects.

(1) Some commercially chips using RISC-V have been released and applied on a large scale.

(2) Performance close to mainstream desktop processors.

(3) A heterogeneous system that composed of mainstream processors and open source processors using RISC-V made.

(4) The operating system transplanted to the RISC-V is more stable and reliable.

(5) Multi-core parallel computing using hundreds of simple RISC-V cores.

(6) RISC-V is used as an example teaching in learning.

(7) The debugging function has been further strengthened.

RISC-V develops very rapidly. In addition to the RISC-V-based open source processors and SoCs that have emerged in large numbers, there are also many commercial processors that plan to adopt the RISC-V, such as PulSAR, which uses a heterogeneous multiprocessor structure, including two scalar processors Rocket, also includes two BOOMs.

On the one hand, the development of RISC-V benefits from its own design, which has absorbed nearly 40 years of experience and lessons from RISC, which makes the architecture design more reasonable. On the other hand, thanks to the increasingly mature software ecology, UCB provides open source compilation for RISC-V GCC, LLVM, also open source emulators Spike, QEMU are provided, further more, the community has transplanted FreeBSD, Debian, Gentoo, Yocto, Genode and other operating systems.