A switching power supply with sufficiently low noise levels to directly power noise-sensitive components

Have you encountered situations where the output results of an ADC exhibit slight deviations and random variations? This may be caused by noise within the ADC system itself. A common source of noise is the power supply rail for the voltage-controlled oscillator (VCO). Noise on this supply rail can introduce jitter to the clock signal, which is subsequently used as the sampling clock for the ADC. Significant jitter may introduce errors in ADC conversions, leading to erroneous data.

It is well known that Switching Mode Power Supplies (SMPS) require switching operations during voltage conversion, inevitably generating noise. Employing an SMPS for the clock supply rail introduces this noise into the ADC system. To minimise errors, noise-sensitive components are typically powered by Low Dropout (LDO) regulators with noise suppression capabilities.

ADI's LTM8080 buck regulator SMPS device integrates a post-regulator dual LDO regulator with noise suppression technology. Similar to the standalone LT3045 LDO regulator, this SMPS device delivers low-noise power rails.

Why is it essential to monitor power rail noise?

Power rail noise is a critical factor capable of significantly impacting system performance. In Figure 1, the LT3045 LDO regulator serves as a low-noise power rail, supplying the VCO of the ADF4372 frequency synthesiser. The ADF4372 then generates clock signals for the AD9208 ADC and the FPGA board. Figure 2 displays the phase noise plot obtained from the output of the LT3045 LDO regulator, which serves as a benchmark for comparing alternative power rail solutions.

Figure 1. Basic Block Diagram of VCO/ADC Configuration

Figure 2. LT3045 phase noise diagram as a reference (1 GHz, 2 MHz sweep)

Compared to the baseline design, employing a higher-noise power rail yields a less favourable noise spectrum, as illustrated in Figure 3, where the sidebands exhibit a slight elevation. When these sidebands reach a certain threshold, they introduce jitter to the rising edge of the ADC sampling clock (Figure 4). Consequently, the ADC samples the analogue input signal at unintended time points, resulting in anomalous data words containing bit errors.

The occurrence of bit errors may have significant consequences, particularly when the errors are severe. The deviation between the actual data word from the ADC and the expected data word may trigger unexpected system behaviour. For instance, if the data word indicates an input voltage higher than the actual voltage, the device may be prematurely activated before the system is prepared. In safety-critical applications, such an unintended state could lead to the disabling of safety features.

Figure 3. Illustrative phase noise diagram for a high-noise SMPS (1.23 GHz, 2 MHz bandwidth)

Thanks to EMI noise shielding technology, the SMPS can now be positioned near the LDO regulator without coupling switching noise to the LDO's output. Packaging the SMPS and LDO regulator together offers additional benefits beyond noise reduction. See Table 1.

Figure 4. High-noise VCO supply rail induces edge jitter in the ADC sampling clock (VCO output), thereby causing ADC sampling errors.

Advantages of integrating switch-mode buck converters and LDO regulators within a single package

Table 1. Advantages of SMPS + LDO Regulators Compared to Standalone LDO Regulators